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Computationally efficient implementation of video rectification in FPGA fo stereo vision applications

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dc.contributor.author Maldeniya, BS
dc.contributor.author Navvarathna, UDU
dc.contributor.author Wijayasekara., KU
dc.contributor.author Wijegoonasekara, TUSW
dc.contributor.author Rodrigo, R
dc.date.accessioned 2013-10-21T02:12:48Z
dc.date.available 2013-10-21T02:12:48Z
dc.identifier.uri http://dl.lib.mrt.ac.lk/handle/123/8222
dc.description.abstract In order to obtain depth perception in computer vision, one needs to process pairs of stereo images. This process is computationally challenging to be carried out in real-time, because it requires the search for matches between objects in both images. Such process is significantly simplified if the images are reflected. Stereo image reflection involves a matrix transformation which when done in software will not produce real-time results. But in stereo vision applications this features is very demanding. On the other hand, applying those transformations to the video frames is very restricted by real-time constraints. Therefore, the video streaming and matrix transformation are not usually implemented in the same system. Our product is a stereo camera pair which produces a rectified real time image output with a resolution of 320x240 at a frame rate of 15FPS and delivers then via 100-Ethernet interface. We use an Spartan 3E FPGA for real-time processing within we implement an image rectification algorithm.
dc.language en
dc.title Computationally efficient implementation of video rectification in FPGA fo stereo vision applications
dc.type Conference-Abstract
dc.identifier.year 2010
dc.identifier.conference Research for Industry
dc.identifier.place Faculty of Engineering, University of Moratuwa
dc.identifier.pgnos 168-173
dc.identifier.proceeding 16th Annual symposium on Research and Industry


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