Show simple item record Abeydeera, M Pasqual, AA 2018-12-19T20:38:26Z 2018-12-19T20:38:26Z
dc.description.abstract The inverse transform function of the HEVC Decoder has grown greatly in complexity with the addition of larger transform sizes and recent works have focused on efficient architectures that can achieve the required throughput. In this work we make the observation that a majority of the coefficients in a typical transform operation is zero, and therefore has no impact on the final outcome. We propose an architecture that can efficiently operate on such sparse matrices and introduce a scheduling strategy which completes a 2D IDCT with bare minimum iterations, with the added advantage of being able to integrate seamlessly with the entropy decoder without a coefficient reordering buffer. Experiments show that although the performance of this approach is scalable with the bit rate, a 120 MHz operating frequency is sufficient to handle QHD @ 48 Mbps, which is less than one third of the frequency requirement of prior work. en_US
dc.language.iso en en_US
dc.title HEVC Inverse transform architecture utilizing coefficient sparsity en_US
dc.type Conference-Abstract en_US
dc.identifier.faculty Engineering en_US
dc.identifier.department Department of Electronic and Telecommunication Engineering en_US
dc.identifier.year 2015 en_US
dc.identifier.conference IEEE International Conference on Image Processing (ICIP) - 2015 en_US Quebec City, QC en_US
dc.identifier.pgnos pp. 4848 - 4852 en_US en_US en_US
dc.identifier.doi 10.1109/ICIP.2015.7351728 en_US

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