High performance parallel packet classification architecture with popular rule caching

Abstract

As the Internet evolves novel services and applications are being introduced which require di erent levels of Quality of Service or non best e ort service for proper functionality. Thus, there is a requirement for future networking equipment to distinguish between tra c ows belonging to di erent applications. The enabling function for such di erentiation is multi eld packet classi cation. Traditional software and hardware approaches to multi eld Packet Classi cation are being challenged due to the exponential growth of internet tra c and data rates. Cur- rent growth rates of silicon technologies will not be able to handle the growth rates of Internet tra c, data rates, and rule database storage requirements in the future. Even though many research have been done in this area, packet classi- cation technologies that support scalability in both line rates and rule sets is scarce. We try to address these issues through a hardware architectural approach for packet classi cation. We identify that classifying multiple packet streams simul- taneously by utilizing immense parallelism o ered by modern hardware technolo- gies while sharing a common rule database among several packet classi cation modules is the solution to the ever widening gap between Internet data rates and silicone speeds. Main contribution of this work is design and implementation of a packet classi cation architecture which has following characteristics: scalability in terms of both throughput and number of rules, capability of classifying parallel packet streams simultaneously, capability of using temporal locality of Internet tra c to increase the classi cation throughput by identifying classi cation rules which are popular among incoming packets and caching them in private caching entities in classi cation modules to avoid contentions at the shared rule database. Simulation results revealed that proposed architecture is capable of achieving a throughput of more than 200Gbps for worst case packet size of 40 bytes. Proposed architecture was implemented on NetFPGA platform and the classi cation was done at full line rate.