Show simple item record Thayaparan, S Nanayakkara, A 2014-06-25T12:46:50Z 2014-06-25T12:46:50Z 2014-06-25
dc.description.abstract This paper analyses the FIFO design for the receiver of 10GBase-X PCS sublayers specified by IEEE 802.3 CSMA/CD Standards. The proposed FIFO design will save the gate count, power and the silicon area in ASIC design considerably. en_US
dc.language.iso en en_US
dc.source.uri en_US
dc.title FIFO design for IEEE 802.3 standard 10GBase-X PCS and XGXS sublayers en_US
dc.type Conference-Abstract en_US
dc.identifier.faculty Engineering en_US
dc.identifier.department Department of Electronic and Telecommunication Engineering, en_US
dc.identifier.year 2013 en_US
dc.identifier.conference International Conference on Intelligent Systems, Modelling and Simulation [4th] - ISMS en_US Bangkok en_US
dc.identifier.pgnos pp. 589-591 en_US en_US

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